1. Field of the Invention
The present invention relates to a semiconductor device adapting a trench gate structure (with a gate buried in a trench), and more particularly to a trench gate type semiconductor device capable of withstanding a high voltage and a manufacturing method of the same.
2. Related Arts
With regard to a semiconductor device serving as an integrated circuit, there have been proposed various structures, in one of which, for example, elements are isolated by a trench provided on a surface of a semiconductor substrate as one of trends for improving in degree of integration and for improving characteristics. On the other hand, as to a semiconductor device serving as a power element or the like, a trench gate structure (with a gate buried in a trench) has been proposed in order to attain lower ON resistance and lower ON voltage.
The present invention relates to the semiconductor devices of the foregoing structures, and has an object to solve technical problems occurring during the fabrication sequence and derived from the structure thereof. The following description will describe prior arts and three technical problems occurring in the prior arts.
First, in a semiconductor device having a MOS structure in a power MOSFET or an IGBT, a diffusion layer for forming a channel is provided by the double diffusion method. This method is also applied to form a channel-forming diffusion layer in the trench gate type semiconductor device.
FIGS. 20A to 20J show a typical fabrication sequence of a conventional trench gate type semiconductor device by use of the double diffusion method. As shown in FIG. 20A, an oxide film 2 serving as a mask material is formed on a semiconductor substrate 1 having a n-type principal surface. Then, p-type impurities (boron, B) are implanted at acceleration energy of approximately 100 keV by ion implantation, whereby an ion implantation layer 3a is formed (FIG. 20B). After that, an island-shaped base region 3 is formed within an element forming region by diffusing the impurities (FIG. 20C).
Next, n-type impurities are implanted at high concentration into the base region. 3 by ion implantation and then diffused, whereby a highly doped emitter region 4 is formed inside the base region 3 (FIG. 20D). A trench 5 is formed by anisotropic etching to the double diffused and highly doped emitter region 4 (FIG. 20E). A gate insulation film 6 is formed over an inner wall surface of the trench 5 (FIG. 20F). Subsequently, a polycrystalline silicon layer 7 is deposited entirely on the substrate (FIG. 20G), which is then etched away except for a portion filling an opening of the trench 5, whereby a gate electrode 8 is formed (FIG. 20H).
Then, a highly doped p-type region 9 is formed inside the base region 3 by introducing p-type impurities at high concentration (FIG. 20I). After that, an insulation film 10 is deposited entirely on the substrate, and is patterned so as to electrically isolate the gate electrode 8. Then, an emitter electrode 11 is formed (FIG. 20J). Further, a metal electrode is formed on a back surface (not shown). Accordingly, a trench gate type MOSFET (with the gate buried in the trench) is fabricated.
FIG. 21 shows an impurity concentration profile (corresponding to a view taken along a line XXI—XXI in FIG. 20J) along a depth direction of a channel portion in a trench gate type semiconductor device which is equivalent to the one shown in FIG. 20J manufactured by the fabrication sequence discussed above. As shown in FIG. 21, the impurity concentration profile in the channel portion (equivalent to the concentration profile of the p-type region) has a sharp pointed concentration profile (a portion indicated by an open arrow in the drawing) at the depth close to the highly doped emitter region 4.
Thus, in case of the trench gate type semiconductor device manufactured by the double diffusion method as described above, a threshold voltage is determined by a maximum impurity concentration in the channel portion, and cut-off characteristic is susceptible to a width of the maximum impurity concentration region. Accordingly, in the prior art in which the width of the maximum impurity concentration region is narrow, a variation of the threshold value, a destruction of the semiconductor device caused by current concentration due to the variation of the threshold value, and deterioration of cut-off characteristics occur.
In addition, in the case that the semiconductor device having the above-described structure is manufactured as a trench gate type IGBT, there is a technical problem as follows.
Namely, in the IGBT having a highly doped p-type region formed on the back surface of the semiconductor substrate 1, there is a parasitic bipolar operation which is known as a problem intrinsic to the IGBT. The bipolar operation depends on a resistance value (hereinafter, referred to as a pinch resistance) of the base region 3 beneath the highly doped emitter region 4. Thus, in the IGBT manufactured by the method in the prior art described above, the pinch resistance increases due to the sharp concentration profile in the channel portion, whereby the parasitic bipolar operation is readily triggered.
Also, as a second technical problem to be solved by the present invention, there is a problem resulted from the prior art as follows. That is, in a conventional trench gate type power semiconductor device capable of withstanding a high voltage, various attempts have been made in efforts to improve the withstand voltage. FIGS. 22A and 22B are schematic cross sectional views each showing a structure of an IGBT as a typical power element. FIG. 22A shows an IGBT, in which a p-type region 12a is formed on the back surface of a semiconductor substrate 12, and the trench gate structures are formed in the manner as described above at a narrow pitch. According to this structure, by narrowing a spacing between the trench gate structures, an electric field developed at the bottom of the trench 5 at the breakdown is alleviated, thereby making it possible to improve a gate withstand voltage.
This arrangement can alleviate the concentration of the electric field. However, the point of concentration of the electric field still exists at the bottom portion of the trench gate structure. Thus, the gate insulation film 6 is damaged by hot carriers due to the concentration of electric field at breakdown. Hence, there is a technical problem that it is difficult to prolong the service life of this element.
On the other hand, FIG. 22B shows an arrangement to improve the withstand voltage not by narrowing the spacing between the trench gate structures, but by providing a structure referred to as a P body. More specifically, the basic arrangement is the same as the one shown in FIG. 22A, but a larger spacing is secured between the adjacent trench gate structures, and a p-type region (hereinafter, referred to as the P body layer) 13 with a deep junction is formed in the spacing region, so that the electric field developed at the bottom portion of the trench gate structure is alleviated, thereby making it possible to improve the withstand voltage.
The IGBT (trench gate type semiconductor device) having the P body structure is manufactured by the fabrication sequence detailed in FIGS. 23A through 23I. More specifically, p-type impurities are implanted into the regions partially at the both sides of a trench forming portion by ion implantation on the surface of the semiconductor substrate 12 (the p-type region 12a on the back surface is omitted herein)(FIG. 23A). The ion implantation is carried out through an oxide film 14 formed on the semiconductor substrate 12, on which a patterned photoresist 15 is provided as a mask. Then, an ion implantation layer 16 is formed partially by selectively implanting the p-type impurities at acceleration energy of approximately 100 keV, which is diffused so as to form the P body layer 13 (FIG. 23B). The following steps (FIGS. 23C through 23I) are the same as those respectively shown in FIGS. 20A through 20J detailing the fabrication sequence of the trench gate structure described above.
In this case, since the P body layer 13 is formed by diffusing the introduced impurities so that the P body reaches a predetermined depth, variation of the threshold value caused by lateral diffusion should be restrained. For this reason, a larger spacing has to be secured between the trench gate electrodes in comparison with the structure of the IGBT shown in FIG. 22A. This limiting factor makes it impossible to improve integration.
Further, a third technical problem will be explained as follows. Namely, a power semiconductor device capable of withstanding a high voltage is provided with a high voltage withstanding structure for alleviating the electric field at a peripheral portion of the element region. FIG. 24 is a cross sectional view showing one example of such a structure. According to this example, a guard ring 16 with a deep junction is provided at the peripheral portion of an island of the base region 3, and multiple strip-wise field limiting rings 17 for alleviating the concentration of the electric field on the surface of the substrate are formed in the n-type substrate region 12 at the periphery of the island shaped base region 3, so that the withstand voltage is improved.
Thus, the structure is provided with the region of the guard ring 16 formed at the periphery of the base region 3 and the region of the plurality of the field limiting rings 17 between the base region 3 and an EQR region at an outermost of the chip. Hence, the concentration of the electric field is alleviated by a deep junction with a large curvature between the base region 3 to which a high voltage is applied and the semiconductor substrate 12 serving as the collector. Moreover, the concentration of the electric field in the surface portion of the substrate is alleviated by a plurality of the field limiting rings 17. As a result, the withstand voltage of the device can be totally improved.
In this case, in the trench gate type IGBT having the P body structure shown in FIG. 22B discussed above, since the p-type guard ring 16 and field limiting rings 17 shown in FIG. 24 can be formed in the same step when the P body layer 13 is formed, the manufacturing cost is not increased. On the other hand, in the narrow pitched trench gate type IGBT shown in FIG. 22A, the step of forming the p-type region with a deep junction is not provided primarily. Therefore, an additional special step is necessary to form the guard ring 16 and field limiting rings 17. Hence, the number of steps in the fabrication sequence is increased, whereby the overall cost is increased.
Further, in either of the structures shown in FIGS. 22A and 22B, the lateral diffusion is inevitable by the forming of the guard ring 16 and the field limiting rings 17 as the p-type regions with a deep junction, whereby the chip size is enlarged. Hence, there is a trade-off between an improvement of the withstand voltage and integration. As a result, one of the functions which is more desirable has to be selected.
After all, in the case that the conventional manufacturing method is adapted, the following problems occur. First, the variation of the threshold value caused by a sharp concentration profile in the channel portion, the destruction of the semiconductor device caused by the current concentration due to the variation of the threshold value, and the deterioration of cut-off characteristics occur. Second, in the IGBT, there are problems that a parasitic bipolar operation is readily-triggered and that the gate insulation film becomes less reliable since the gate insulation film is damaged by the hot carriers caused by the electric field concentrates at the bottom portion of the trench when the breakdown has occurred. Moreover, there is a problem that the manufacturing cost increases by providing with the high voltage withstanding structures.